Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.2.76. IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF

Instructs Analysis & Synthesis to ignore all translate_off/synthesis_off synthesis directives in your Verilog and VHDL design files. You can use this option to disable these synthesis directives and include previously ignored code during elaboration.

Type

Boolean

Device Support

This setting can be used in projects targeting any Altera device family.

Notes

This assignment is included in the Analysis & Synthesis report.

Syntax


		set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF <value>
	

Default Value

Off

Example


		set_global_assignment -name ignore_translate_off_and_synthesis_off on