Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.10.38. CVP_MODE

Specifies the configuration mode for Configuration via Protocol (CvP). In Core initialization mode, the periphery image is stored in an external configuration device and is loaded into the FPGA through the conventional configuration scheme. The core image is stored in a host memory and is loaded into the FPGA through the PCIe link. In core update mode, the FPGA device is initialized after initial system power up by loading the full configuration image from the external local configuration device to the FPGA. User can use the PCIe link to perform one or more FPGA core image update through this mode. In the Off mode, CvP is turned off.

Old Name

CVPCIE_MODE

Type

Enumeration

Values

  • Core initialization
  • Core initialization and update
  • Core update
  • Off

Device Support

  • Arria 10
  • Arria V
  • Arria V GZ
  • Cyclone V
  • Stratix V

Notes

None

Syntax


		set_global_assignment -name CVP_MODE <value>
	

Default Value

Off

Example


		set_global_assignment -name CVP_MODE "Power up and subsequent core configuration"