Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.10.177. INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY

Increases the propagation delay from the interior of the device to the clock enable input of an output enable register. This is an advanced option that should be used only after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory. This option is ignored if it is applied to anything other than an I/O cell that has an output enable register with a clock enable signal. For detailed information on how to use this option, refer to the data sheet for the device family, which is available from the Literature section of the Altera web site.

Old Name

INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR

Type

Enumeration

Values

  • Large
  • Off
  • On
  • Small

Device Support

  • Stratix
  • Stratix GX

Notes

This assignment supports Fitter wildcards.

Syntax


		set_instance_assignment -name INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY -to <to> -entity <entity name> <value>