Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.2.156. USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING

Directs the compiler to use LogicLock constraints during DSP and RAM balancing.

Type

Boolean

Device Support

This setting can be used in projects targeting any Altera device family.

Notes

This assignment is included in the Analysis & Synthesis report.

Syntax


		set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING <value>
	

Default Value

On

Example


		set_global_assignment -name use_logiclock_constraints_in_balancing on