Altera® Quartus® Prime Standard Edition Settings File Reference Manual
Visible to Intel only — GUID: qly1489537834185
Ixiasoft
Visible to Intel only — GUID: qly1489537834185
Ixiasoft
1.8.16. EDA_GENERATE_FUNCTIONAL_NETLIST
Generate Verilog/VHDL netlist for functional or timing simulation with EDA simulation tools. When this option is 'On', the EDA Netlist Writer does not generate a Standard Delay Format Output File (.sdo). If the device does not support timing simulation, then only the functional-simulation netlist is available.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -section_id <section identifier> <value>
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier