Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.2.8. ALLOW_SYNCH_CTRL_USAGE

Allows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.

Type

Boolean

Device Support

  • Arria 10
  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Arria V
  • Arria V GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • Cyclone V
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • MAX II
  • MAX V
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV
  • Stratix V

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax


		set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE <value>
		set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity <entity name> <value>
		set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to <to> -entity <entity name> <value>
	

Default Value

On

Example


		set_global_assignment -name allow_synch_ctrl_usage off
		set_instance_assignment -name allow_synch_ctrl_usage off -to foo
	

See Also

Force Use of Synchronous Clear Signals