Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.2.33. CLKLOCKX1_INPUT_FREQ

Creates an internal ClockLock phase-locked loop (PLL) and specifies its frequency. Turning this option on is equivalent to instantiating an altclklock megafunction with either of its ClockBoost parameters set to a value of 1. The CLKLOCKx1 Input Frequency option is provided primarily for backward compatibility with MAX+PLUS II designs. Altera recommends using the MegaWizard Plug-In Manager to instantiate PLLs in new designs. This option is ignored if it is assigned to anything other than an input pin or to a device that does not have the PLL feature.

Type

Frequency

Device Support

  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • A
  • E
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • Mercury
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV

Notes

None

Syntax


		set_instance_assignment -name CLKLOCKX1_INPUT_FREQ -to <to> -entity <entity name> <value>