Visible to Intel only — GUID: ugk1489537871824
Ixiasoft
Visible to Intel only — GUID: ugk1489537871824
Ixiasoft
1.10.15. AUTO_GLOBAL_REGISTER_CONTROLS
Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding clock signals) as global signals that are made available throughout the device on the global routing paths. Depending on the target device family, these control signals can include asynchronous clear and load, synchronous clear and load, clock enable, and preset signals.If you want to prevent the Compiler from automatically selecting a particular signal as global register control signal, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
- Virtual JTAG TAP
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS <value>
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -to <to> -entity <entity name> <value>
Default Value
On