Visible to Intel only — GUID: vlh1489537979849
Ixiasoft
Visible to Intel only — GUID: vlh1489537979849
Ixiasoft
1.10.283. QII_AUTO_PACKED_REGISTERS
Allows the Compiler to combine a register and a combinational function, or to implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option controls how aggressively the Fitter combines registers with other function blocks to reduce the area of the design. Generally, the 'Auto' or 'Sparse Auto' settings should be used for this option. The other options limit the flexibility of the Fitter to combine registers with other function blocks and can result in no fits. When 'Auto', the default setting is selected, the Fitter attempts to achieve the best performance with good area. If necessary, additional logic is combined to reduce the area of the design so that it can fit within the selected device. When this setting is 'Sparse Auto', the Fitter attempts to achieve the highest performance with possibly increased area, but without exceeding the logic capacity of the device. If this option is set to 'Off', the Fitter does not combine registers with other functions. The 'Off' setting severely increases the area of the design and may cause a no fit. If this option is set to 'Sparse', the Fitter combines functions in a way which improves performance for many designs. If this option is set to 'Normal', the Fitter combines functions that are expected to maximize design performance and reduce area. When this option is set to 'Minimize Area', the Fitter aggressively combines unrelated functions to reduce the area required for placing the design, at the expense of performance. When this option is set to 'Minimize Area with Chains', the Fitter even more aggressively combines functions that are part of register cascade chains or can be converted to register cascade chains. If this option is set to any value but 'Off', registers are combined with I/O cells to improve I/O timing (as long as the Optimize IOC Register Placement For Timing option allows it), and with DSP blocks and RAM blocks to reduce the area required for placing the design or to improve timing when possible.
Old Name
AUTO_PACKED_REGISTERS_ARMSTRONG, AUTO_PACKED_REGISTERS_STRATIXII, Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX
Type
Enumeration
Values
- Auto
- Minimize Area
- Minimize Area with Chains
- Normal
- Off
- Sparse
- Sparse Auto
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name QII_AUTO_PACKED_REGISTERS <value>
set_global_assignment -name QII_AUTO_PACKED_REGISTERS -entity <entity name> <value>
set_instance_assignment -name QII_AUTO_PACKED_REGISTERS -to <to> -entity <entity name> <value>
Default Value
Auto