GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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4.12. Transaction Layer Packet (TLP) Bypass Mode

The GTS AXI Streaming IP includes a TLP Bypass mode for both downstream and upstream ports to allow the implementation of advanced features such as:
  • The upstream port or the downstream port of a switch.
  • A custom implementation of a Transaction Layer to meet specific user requirements.

When the TLP Bypass feature is enabled, the PCIe* Hard IP does not process received TLPs internally but outputs them to the user application. This allows the application to implement a custom Transaction Layer. In the TLP Bypass mode, the PCIe* Hard IP does not generate/check the ECRC and does not remove it if the received TLPs has the ECRC by default.

The GTS AXI Streaming IP in TLP Bypass mode still includes some of the PCIe* configuration space registers related to link operation. It interfaces with the application logic via the AXI-Stream interface (for all TLP traffic), the AXI-Lite interface (for Lite TL's configuration registers access) and other miscellaneous signals.

In the TLP Bypass mode, the PCIe* Hard IP supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code. However, in the TLP Bypass mode, Configuration-via-Protocol (CvP) is not supported.

Figure 28.  TLP Bypass Mode