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1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP
3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Precision Time Measurement (PTM)
4.11. Single Root I/O Virtualization (SR-IOV)
4.12. Transaction Layer Packet (TLP) Bypass Mode
4.13. Scalable IOV
6.1. Overview
6.2. Clocks and Resets
6.3. AXI4-Stream Interfaces
6.4. Configuration Intercept Interface
6.5. Control Shadow Interface
6.6. Transmit Flow Control Credit Interface
6.7. Completion Timeout Interface
6.8. Control and Status Register Responder Interface
6.9. Function Level Reset Interface
6.10. TLP Bypass Error Reporting Interface
6.11. VF Error Flag Interface
6.12. Precision Time Measurement (PTM) Interface
6.13. Serial Data Signals
6.14. Miscellaneous Signals
7.4.1.1. GTS AXI Streaming IP Version
7.4.1.2. GTS AXI Streaming IP Features
7.4.1.3. GTS AXI Streaming IP Interface Attributes
7.4.1.4. LEGACY INTERRUPT CTRL
7.4.1.5. CFG REG IA CTRL
7.4.1.6. CFG REG IA FN NUM
7.4.1.7. CFG REG IA WRDATA
7.4.1.8. CFG REG IA RDDATA
7.4.1.9. PRS CTRL
7.4.1.10. MSI PENDING CTRL
7.4.1.11. MSI PENDING
7.4.1.12. D-STATE STS
7.4.1.13. CFG RETRY CTRL
7.4.3.1. PERFMON CTRL
7.4.3.2. TX MRD TLP
7.4.3.3. TX MWR TLP
7.4.3.4. TX MSG TLP
7.4.3.5. TX CFGWR TLP
7.4.3.6. TX CFGRD TLP
7.4.3.7. RX MRD TLP
7.4.3.8. RX MWR TLP
7.4.3.9. RX MSG TLP
7.4.3.10. RX CFGWR TLP
7.4.3.11. RX CFGRD TLP
7.4.3.12. TX MEM DATA
7.4.3.13. TX CPL DATA
7.4.3.14. RX MEM DATA
7.4.3.15. RX CPL DATA
7.6.1. VF PCI-Compatible Configuration Space Header Type0
7.6.2. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
7.6.3. VF PCI Express* Capability Structure
7.6.4. VF Alternative Routing ID (ARI) Capability Structure
7.6.5. VF Transaction Processing Hints (TPH) Capability Structure
7.6.6. VF Address Translation Services (ATS) Capability Structure
7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.3.1. PCI Express* Capability List Register
7.6.3.2. PCI Express* Device Capabilities Register
7.6.3.3. PCI Express* Device Control and Status Register
7.6.3.4. Link Capabilities Register
7.6.3.5. Link Control and Status Register
7.6.3.6. PCI Express* Device Capabilities 2 Register
7.6.3.7. PCI Express* Device Control and Status 2 Register
7.6.3.8. Link Capabilities 2 Register
7.6.3.9. Link Control and Status 2 Register
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A.1.1. Debugging Link Training Issues
The Physical Layer automatically performs link training and initialization without software intervention. This is a well-defined process to configure and initialize the device's Physical Layer and link so that PCIe* packets can be transmitted.
Some examples of link training issues include:
- Link fails to negotiate to expected link speed.
- Link fails to negotiate to the expected link width.
- LTSSM fails to reach/stay stable at L0.
Figure 66. Link Training Debugging Flow
Note: (*) Redo the equalization using the Link Equalization Request 8.0 GT/s bit of the Link Status 2 register for 8.0 GT/s or Link Equalization Request 16.0 GT/s bit of the 16.0 GT/s Status Register.
Use the following debug tools for debugging link training issues observed on the PCI Express* link when using the GTS AXI Streaming IP.