GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

4.6. Transaction Ordering

The GTS AXI Streaming IP does not have separate receiving queues to handle PCIe* transaction ordering or prevent deadlocks.

The application logic needs to ensure the transactions adhere to PCIe ordering rules that prevent deadlocks, namely:
  • Allow posted writes to pass blocked read transactions.
  • Allow posted writes to pass blocked configuration write transactions.
  • Allow completion to pass blocked read transactions.
  • Allow completion to pass blocked configuration write transactions.