GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

7.4.2.1. HIP Status

Default value: 0x0000_0000

Table 83.  HIP Status Register
Register Name Bit Location Attribute User Side Description
HIP Status 0 ROS

Link Up Indication.

  • 0: Link Down
  • 1: Link up
1 ROS

Data Link Layer Active Indication.

  • 0: DL not Active
  • 1: DL Active
7:2 ROS

Indicates LTSSM State.

  • 6'h00: S_DETECT_QUIET
  • 6'h01: S_DETECT_ACT
  • 6'h02: S_POLL_ACTIVE
  • 6'h03: S_POLL_COMPLIANCE
  • 6'h04: S_POLL_CONFIG
  • 6'h05: S_PRE_DETECT_QUIET
  • 6'h06: S_DETECT_WAIT
  • 6'h07: S_CFG_LINKWD_START
  • 6'h08: S_CFG_LINKWD_ACCEPT
  • 6'h09: S_CFG_LANENUM_WAIT
  • 6'h0A: S_CFG_LANENUM_ACCEPT
  • 6'h0B: S_CFG_COMPLETE
  • 6'h0C: S_CFG_IDLE
  • 6'h0D: S_RCVRY_LOCK
  • 6'h0E: S_RCVRY_SPEED
  • 6'h0F: S_RCVRY_RCVRCFG
  • 6'h10: S_RCVRY_IDLE
  • 6'h11: S_L0
  • 6'h12: S_L0S
  • 6'h13: S_L123_SEND_EIDLE
  • 6'h14: S_L1_IDLE
  • 6'h15: S_L2_IDLE
  • 6'h16: S_L2_WAKE
  • 6'h17: S_DISABLED_ENTRY
  • 6'h18: S_DISABLED_IDLE
  • 6'h19: S_DISABLED
  • 6'h1A: S_LPBK_ENTRY
  • 6'h1B: S_LPBK_ACTIVE
  • 6'h1C: S_LPBK_EXIT
  • 6'h1D: S_LPBK_EXIT_TIMEOUT
  • 6'h1E: S_HOT_RESET_ENTRY
  • 6'h1F: S_HOT_RESET
  • 6'h20: S_RCVRY_EQ0
  • 6'h21: S_RCVRY_EQ1
  • 6'h22: S_RCVRY_EQ2
  • 6'h23: S_RCVRY_EQ3
8 ROS

User Mode.

  • 0: HIP is in non-user mode
  • 1: HIP in User Mode
9 ROS

HIP PLD Interface Ready Indication.

  • 0: HIP PLD Interface not Ready
  • 1: HIP PLD Interface Ready
10 ROS

HIP Entered in Error Mode.

  • 0: Normal Operation
  • 1: RAM ECC Error Detected by HIP
11 RW1C

HIP Buffer Overflow.

  • 1: Indicates HIP Buffer Overflow Issue
12 RsvdZ Reserved.
13 RsvdZ Reserved.
31:14 RsvdZ Reserved.