GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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7.6.4.1. ARI Enhanced Capability Header Register

Address: Offset 0x0

This register contains the PCI Express* Extended Capability ID for ARI, the capability version, and the pointer to the next capability structure.

Table 119.  ARI Enhanced Capability Header Register Description
Bit Location Description Attributes Default
15:0 PCI Express* Extended Capability ID for ARI. RO Same as parent PF
19:16 Capability Version. RO Same as parent PF
31:20

Next Capability Pointer.

When TPH Requester Capability is present, points to TPH.

When ATS Capability is present, but TPH Requester Capability is not, points to ATS.

When neither TPH Requester Capability nor ATS Capability is present, its value is 0.

RO Programmable