GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

A.2.1. Overview

The Agilex™ 5 Debug Toolkit is a System Console-based tool that provides real-time control, monitoring and debugging of the PCIe* links at the Physical Layer.

The Agilex™ 5 Debug Toolkit allows you to:

  • View protocol and link status of the PCIe* links.
  • View PLL and per-channel status of the PCIe* links.
  • View the channel analog settings.
  • Indicate the presence of a re-timer connected between the link partners.
Note: The current version of Quartus® Prime supports enabling the Debug Toolkit for the Endpoint mode only, and with the Linux and Windows operating systems only.

The following figure provides an overview of the Agilex™ 5 Debug Toolkit in the GTS AXI Streaming IP.

Figure 68. Overview of the Agilex™ 5 Debug Toolkit

When you enable the Agilex™ 5 Debug Toolkit, the GTS AXI Streaming IP module of the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.

Drive the Debug Toolkit from a System Console. The System Console connects to the Debug Toolkit via an Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel® FPGA Download Cable.

When the Debug Toolkit is enabled, a multiplexer is implemented to allow switching between the Control and Status Register Responder Interface and the System Console-based Debug Toolkit. This allows you to switch between the user logic driving the Control and Status Register Responder Interface and the Debug Toolkit, as both access the same set of registers within the Hard IP.

Note: The Control and Status Register Responder Interface has the default access (the default is when toolkit_mode = 0). Upon launching the Debug Toolkit from System Console, toolkit_mode is automatically set to 1 for DTK access. Upon exiting (closing) the Debug Toolkit window of the System Console, toolkit_mode is automatically set to 0 for user access.

The Debug Toolkit is launched successfully only if pending read/write transactions on the Control and Status Register Responder Interface are completed (as indicated by the deassertion of the reconfig_waitrequest signal).

Note: Upon being launched from System Console, the Debug Toolkit will first check if any of the waitrequest signals from the Hard IP is asserted (which means there is an ongoing request from you). The System Console message window shows an error message to let you know there is an ongoing request and the Debug Toolkit cannot be launched.

Provide a clock source (100 MHz–250 MHz) to drive the axi_lite_clk clock. Use the output of the Reset Release Intel® FPGA IP to drive the ninit_done, which provides the reset signal to the NPDME module.