GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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4.11.1. SR-IOV Implementation

Accessing VF PCIe* Information

The PCIe* configuration space for VFs is not directly available to the user application. Your applications can use the following methods to retrieve necessary information (bus master enable, MSI-X, and others):
  • Monitor specific VF registers using the Configuration Intercept Interface (CII) or Configuration Shadow Interface (CSI)
  • Read/write specific VF registers using the AXI-Lite CSR Interface

VF IDs are calculated within PCIe* Hard IP. Your application has header metadata with the TLP to identify the associated VFs within the PFs.

BDF Assignment

When SR-IOV is enabled, the ARI capability is always enabled. The PCIe* Hard IP automatically calculates the completer/requester ID on the Transmit side. Your application needs to provide the VF and PF information in the Header metadata as described in the header format section.

VF Error Reporting

The VFs, with no AER support, are required to generate Non-Fatal error messages. The IP does not generate any error message. It is up to your application logic to generate appropriate messages when specific error conditions occur. The Header metadata makes necessary signals available to the user application logic to generate these messages. The Completion Timeout Interface and VF Error Flag Interface provide the necessary information to generate Non-Fatal error messages.

VF to PF Mapping

VF to PF mapping always starts from the lowest possible PF number. For instance, if the IP has 2 PFs, wherein PF0 has 64 VFs and PF1 has 16 VFs, VF1 to VF64 are mapped to PF0, and VF65 to VF80 are mapped to PF1.

Currently, the IP core only supports the following PF/VF combinations.

Table 21.  PF/VF Combinations Supported
Number of PFs Number of VFs per PF [PF0/PF1] Total VFs
1 8 8
1 16 16
1 32 32
1 64 64
2 16/16 32
2 32/32 64
2 32/0 32
2 0/32 32
2 64/0 64
2 0/64 64
2 128/128 256
2 64/0 64
2 0/64 64
2 128/0 128
2 0/128 128
2 256/0 256
2 0/256 256
4 128/0/0/0 128
4 0/128/0/0 128
4 256/0/0/0 256
4 0/256/0/0 256

For example, the row that shows the combination of 2 PFs, 64 VFs, and the notation 64/0 in the Number of VFs per PF column indicates that all 64 VFs are mapped to PF0, while no VF is mapped to PF1. The SR-IOV permutations allow any PF to be assigned the initial VF allocation.