GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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4.3. PCIe* Hard IP

The PCIe* Hard IP implements the functionality of the PCIe* protocol. The Hard IP implements Physical, Data Link, and Transaction Layers of the protocol. The Hard IP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SR-IOV functionality for virtualization applications.

Figure 10.  Agilex™ 5 PCIe* Hard IP Block Diagram