GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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6.9. Function Level Reset Interface

The FLR (Function Level Reset) interface is used to reset individual Single Root I/O Virtualization (SR-IOV) functions. The PCIe* Hard IP supports FLR for both Physical Functions (PFs) and Virtual Functions (VFs). When an FLR is executed for a specific VF, the packets received for that VF become invalid.

The FLR interface signals are provided to the application interface for managing these resets. The assertion of the flrrcvd_tvalid signal indicates that an FLR has been received for a particular PF or VF. The application logic is then responsible for executing its FLR routine and reporting the completion status back to the Function Level Reset Completion interface.

Before this completion event, the PCIe* Hard IP responds to all transactions for the function undergoing FLR with completions that have an Unsupported Request (UR) status. The PCIe* Hard IP does not implement a timeout for this handshake, so the application must send FLR completion for any FLR request received on the Function Level Reset Received interface.