Visible to Intel only — GUID: dis1711334960573
Ixiasoft
Visible to Intel only — GUID: dis1711334960573
Ixiasoft
6.12. Precision Time Measurement (PTM) Interface
The GTS AXI Streaming IP provides a wires interface for PTM handshake only when operating in Endpoint mode.
The PTM signals require accurate transfer latency so that compensation is done on the receiving end to get the best PTM accuracy. Hence, the PTM signals are in wires and clocked by coreclkout_hip instead of the AXI clock as the AXI clock can change speed due to fabric fmax and require clock crossing.
The GTS AXI Streaming IP flop stages of the PTM value from Tiles to Apps interface are required to be converted to correction values and append on top of the corrections value provided by the Tiles interface. This correction value is used as the final time adjustment to PTM value at destinations. The application manually triggers the PTM context update requests through the wire interface.
Signal Name | Direction | Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) | Clock Domain | Description |
---|---|---|---|---|
p0_ptm_context_valid | Output | EP | coreclkout_hip_toapp | Asserted when PTM context is valid. Rate change, link state change, or error in the received PTM message causes ptm_context_valid to be invalidated. |
p0_start_ptm_newclk_value | Output | EP | coreclkout_hip_toapp | Asserted high for one clock. Indicates start of a new PTM clock value. |
p0_ptm_newclk_value | Output | EP | coreclkout_hip_toapp | Serialized output for the PTM clock value. Valid for 64 clock cycles starting with start_ptm_newclk_value assertion. The LSB of the snapshot is serialized first. |
p0_ptm_clock_correction | Output | EP | coreclkout_hip_toapp | Serialized output for the PTM correction value. Valid for 64 clock cycles starting with start_ptm_newclk_value assertion. The LSB of the snapshot is serialized first. The PTM clock correction is used to indicate the amount by which the new PTM clock value has been corrected. ART can use this to delay the local clock counter in the FPGA. |
p0_ptm_manual_update | Input | EP | coreclkout_hip_toapp | Application asserts this signal to manually trigger the PTM time update within the PCIe* controller. |
The figure below shows a timing diagram for both automatic PTM updates to the application and manual update requests from the application.