GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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6.3.2. AXI4-Stream Transmit (TX) Interface

The outbound packet towards the link from application side is transmitted through this interface. The interface supports data widths of 16 bytes (128 bits), 32 bytes (256 bits), and 64 bytes (512 bits). The TLP header, function number of TLP, and prefix signals are sent in line with data.

Table 37.   AXI4-Stream TX Interface
Signal Name Direction Clock Domain Description
p0_app_ss_st_tx_tvalid Input p0_axi_st_clk Indicates that the remote transmit interface is driving a valid transfer.
p0_ss_app_st_tx_tready Output p0_axi_st_clk Indicates that the receive interface can accept a transfer in the current cycle.
p0_app_ss_st_tx_tdata[(a-1):0] Input p0_axi_st_clk Data bus used to provide the data that is passing across the interface.
p0_app_ss_st_tx_tkeep[(a/8-1):0] 2 Input p0_axi_st_clk

A byte qualifier used to indicate whether the content of the associated byte is valid.

The invalid bytes are allowed only during p0_app_axi_st_tx_tlast cycle.

The sparse p0_app_axi_st_tx_tkeep is not allowed.

p0_app_ss_st_tx_tlast Input p0_axi_st_clk Indicates end of data/command transmission.

The timing diagrams in the following sections are for the simple packing scheme only.

The following figure shows timing diagram for command with data. The completion, memory write, messages, and the configuration write commands fall under command with data category.

The first command transfers a payload of 64 Bytes. The receive interface is ready to accept command at clock cycle 1 but the transmit interface does not have any command to transfer in that same cycle. The transmit interface starts the transfer in the next cycle.

The second command transfers a payload of 128 Bytes. Here, the receive interface is not ready to accept command when the transmit interface has asserted valid. The transmit interface holds information on the bus till it observes ready from the receive interface.

Figure 44.  AXI4-Stream TX Interface—Simple Packing Scheme Timing Diagram (Command With Data)

The following figure shows timing diagram for command with data followed by command without data. The completion, memory write, messages and configuration write commands fall under command with data category. The memory read, configuration read, messages without data and completion without data fall under command without data category.

The first command transfers a payload of 64 Bytes. The receive interface is ready to accept command at clock cycle 1 but the transmit interface does not have any command to transfer in that same cycle. The transmit interface starts the transfer in the next cycle.

The second command is a command without data. Here, the receive interface is not ready to accept command when the transmit interface has asserted valid. The transmit interface holds information on the bus till it observes ready from the receive interface.

Figure 45.  AXI4-Stream TX Interface—Simple Packing Scheme Timing Diagram (Command With Data and Command)

The first command transfers the payload of 67 Bytes.

Note: tkeep during tlast has partial ones, but these ones are contiguous, sparse tkeep is not allowed. The partial tkeep is allowed only on tlast cycle.

The second command is a command without data.

Figure 46.  AXI4-Stream TX Interface—Simple Packing Scheme Timing Diagram (Back-to-Back Commands With and Without Data)
2 For the recommended a value, refer to the Variables Used in the Bus Indice table. 2