GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP

Following is the process to configure and generate the GTS Reset Sequencer Intel® FPGA IP.
  1. Select GTS Reset Sequencer Intel® FPGA IP in the IP Catalog.
  2. A New IP Variant window appears. Specify a top-level name for your new custom IP variation. The Parameter Editor saves the IP variation settings in a file named <your_ip>.ip.
  3. Click Create. The Parameter Editor appears. Set the number of banks and lanes.
  4. Only one GTS Reset Sequencer IP instantiation is required for all the PCIe* and non- PCIe* channels on a side of the device. Set the Number of Lane based on the total number of non- PCIe* channels on the side of the device used in the design. The number of PCIe* channels are not counted in the Number of Lane parameters.
Note: For more descriptions of connecting the GTS Reset Sequencer Intel® FPGA IP, refer to the Implementing the GTS Reset Sequencer Intel® FPGA IP section in the GTS Transceiver PHY User Guide .