GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

4. IP Architecture and Functional Description

This chapter describes the architecture details of the GTS AXI Streaming IP and details the various blocks and modes available in the IP that you can use.
The GTS AXI Streaming IP consists of the following major sub-blocks:
  • PCIe* Hard IP (HIP) which consist of PMA, PCS, PIPE, PCIe* x4 controller, and PLD interface.
  • Soft logic blocks in the FPGA fabric to serve as an adapter between User Logic and HIP to allow user to configure the IP and access to the features supported by HIP. Besides, it also implements functions such as VirtIO, and others.
Figure 5.  GTS AXI Streaming IP Block Diagram

The HIP implements Physical, Data Link and Transaction Layers of the PCIe* protocol. The HIP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SR-IOV functionality for handling virtualization. The System PLL generates the clock to drive the PLD interface and the output clock to drive application logic.

There are reference clock pins and System PLL in each transceiver bank, and PERST pins in the HVIO banks to enable independent PCIe* link in each transceiver bank. Only one PCIe* link allowed in each GTS bank. A PCIe* link is not allowed to straddle across two banks. When a PCIe* link is configured as x1 or x2 mode, remaining channels in the same bank can be configured as non- PCIe* channels. System PLL for the non- PCIe* channels comes from other GTS bank.

Figure 6.  PCIe* Link and Lanes Placements
Note: For details of System PLL output clock network, refer to Implementing the GTS System PLL Clocks Intel® FPGA IP section in GTS Transceiver PHY User Guide