GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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7.6.3.3. PCI Express* Device Control and Status Register

Address: Offset 0x8

This register contains control and status bits for the Function.

Table 115.   PCI Express* Device Control and Status Register Description
Bit Location Description Attributes Default
14:0 Reserved RsvdZ 0
15

Function-Level Reset.

Writing a 1 into this bit position generates a Function-Level Reset for this Virtual Function if the FLR Capable bit of the Device Capabilities Register is set. This bit always reads as 0.

RW 0
16 Reserved RsvdZ 0
17 Non-Fatal Error Detected. RW1C 0
18 Reserved RsvdZ 0
19 Unsupported Request Detected. RW1C 0
20 AUX Power Detected. RO 0
21

Transaction Pending.

Indicates that a Non-Posted request issued by this Virtual Function is still pending.

RO 0
31:22 Reserved RO 0