Visible to Intel only — GUID: vfx1697005940995
Ixiasoft
Visible to Intel only — GUID: vfx1697005940995
Ixiasoft
7.2. PCI Express* Configuration Space
In addition to accessing the Endpoint's configuration space registers by sending Configuration Read/Write TLPs, the AXI-Lite CSR interface also provides read/write access to these registers.
The PCIe* Configuration Space Registers table describes the registers for each PF. To calculate the address for a particular register in a particular PF, add the offset for that PF from the Configuration Space Offsets table to the byte address for that register as given in the PCIe* Configuration Space Registers table.
Byte Address | Configuration Space Register | Corresponding Section in PCIe* Specification |
---|---|---|
0x000 : 0x03C | PCI* Header Type 0/1 Configuration Registers | Type 0/1 Configuration Space Header |
0x040 : 0x044 | Power Management | PCI* Power Management Capability Structure |
0x050 : 0x064 | MSI Capability | MSI Capability Structure, see also PCI* Local Bus Specification |
0x070 : 0x0A0 | PCI* Express Capability | PCI Express* Capability Structure |
0x0B0 : 0x0B8 | MSI-X Capability | MSI-X Capability Structure, see also PCI* Local Bus Specification |
0x0BC : 0x0FC | Reserved | N/A |
0x100 : 0x144 | Advanced Error Reporting (AER) | Advanced Error Reporting Capability Structure |
0x148 : 0x160 | Virtual Channel Capability | Virtual Channel Capability Structure |
0x164 : 0x16C | Device Serial Number Capability | Device Serial Number Capability Structure |
0x174 : 0x178 | Alternative Routing-ID Implementation (ARI) | ARI Capability Structure |
0x184 : 0x194 | Secondary PCI Express* Extended Capability Header | PCI Express* Extended Capability |
0x1A4 : 0x1C4 | Physical Layer 16.0 GT/s Extended Capability |
Physical Layer 16.0 GT/s Extended Capability Structure |
0x1C8 : 0x1DC | Margining Extended Capability | Margining Extended Capability Structure |
0x1E0 : 0x21C | SR-IOV Capability | SR-IOV Capability Structure |
0x220 : 0x228 | TLP Processing Hints (TPH) Capability | TLP Processing Hints (TPH) Capability Structure |
0x2AC : 0x2B0 | Address Translation Services (ATS) Capability | Address Translation Services Extended Capability (ATS) in Single Root I/O Virtualization and Sharing Specification |
0x2BC : 0x2C4 | Access Control Services (ACS) Capability | Access Control Services (ACS) Capability |
0x2C8 : 0x2D4 | Page Request Services (PRS) Capability | Page Request Services (PRS) Capability |
0x2D8 : 0x2DC | Latency Tolerance Reporting (LTR) Capability | Latency Tolerance Reporting (LTR) Capability |
0x2E0 : 0x2E4 | Process Address Space (PASID) Capability | Process Address Space (PASID) Capability Structure |
0x2E8 : 0x3D0 | RAS D.E.S. Capability (VSEC) | — |
0x42C : 0x434 | Precision Time Management (PTM) Capability | Precision Time Management (PTM) Capability |
0x438 : 0x49C | PTM Requestor Capability Structure (VSEC) | — |
0x420 : 0x428 | Data Link Feature Extended Capability | Data Link Feature Extended Capability |
0xD00 : 0xD58 | Intel-defined VSEC | — |