GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

7.2.2. PCI Express* Capability Structures

The layouts of the most basic capability structures are provided below. Refer to the PCI Express* Base Specification for more information about these registers.

Figure 72. Power Management Capability Structure—Byte Address Offsets and Layout
Figure 73. MSI Capability Structure
Figure 74.  PCI Express* Capability Structure—Byte Address Offsets and Layout
Figure 75. MSI-X Capability Structure
Figure 76.  PCI Express* AER Extended Capability Structure

Refer to the Excel-based GTS AXI Streaming IP for PCI Express* Register Map for the detailed descriptions of the registers.