GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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7.4.2.3. HIA BP CYCLES

The register indicates back pressure cycles observed because the HIP interface adaptor transmit interface was not ready to accept transactions.

Default value: 0x0000_0000

Table 85.  HIA BP Cycles Register
Register Name Bit Location Attribute User Side Description
HIA BP CYCLES 30:0 RW1C Back Pressure Cycle Count.
31 RW1C Indicates Overflow, cycle count reached 31'h7FFFFFFFF.