Visible to Intel only — GUID: dtn1696958196359
Ixiasoft
Visible to Intel only — GUID: dtn1696958196359
Ixiasoft
6.5. Control Shadow Interface
The control shadow interface brings out the settings of the various configuration register fields of the function. These fields are mandatory to design the control path of the application layer logic.
The application logic decodes information provided on this interface to create a shadow copy. The interface provides update to primary control signals only. The application logic must read extra information required through the AXI4-Lite Control and Status Register Responder interface by reading configuration register of interest.
Function | Description |
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Bus Master Enable |
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MSI-X Mask |
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MSI-X Enable |
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MemSpace Enable |
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ExpRom Enable | It indicates whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b, the Function's expansion ROM address space is disabled. When the bit is 1b, the address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register. |
TPH Req Enable |
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ATS Enable |
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MSI Enable |
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MSI Mask | It indicates the Function supports MSI Per-Vector Masking when set and not supported when clear. |
Extended Tag | It indicates 8-bit Tag field generation is enabled when set and 5-bit Tag field generation when clear. |
10bit Tag Req Enable | It indicates that the Requester is permitted to use 10-Bit Tags when set, not permitted when clear. |
PTM Enable | It indicates that a Function is permitted to participate in the PTM mechanism according to its selected roles when set and not permitted when it is cleared. |
Maximum Payload Size (MPS) |
The defined encodings are:
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Maximum Read Request Size (MRRS) |
The defined encodings are:
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Virtual Function (VF) Enable |
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Page Request Enable | It indicates that the Page Request Interface is allowed to make page requests when set, not allowed when clear. |
Signal Name | Direction | Clock Domain | Description |
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p0_ss_app_st_ctrlshadow_tvalid | Output | p0_axi_lite_clk | The GTS AXI Streaming IP asserts this output for one clock cycle when there is an update to the register fields being monitored, because of a Configuration Write performed by the root complex. You can copy the new settings of the register fields from the tdata bus. |
p0_ss_app_st_ctrlshadow_tdata[39:0] | Output | p0_axi_lite_clk | When app_ctrl_shadow_tvalid has been asserted, this output provides the current settings of the register fields of the associated Function.
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