GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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6.6. Transmit Flow Control Credit Interface

The link partner's receive buffer space information is provided to application through the Transmit Flow Control Credit Interface. The credits are advertised as the limit value as specified in the PCIe* specification. Apart from the AXI-Stream ready-valid handshake, the application transmits packet only when link partner receive buffer has enough space to accept the TLP. The interface provides posted, non-posted, completion data, and header credit information. One data credit is equal to four dwords (DWs) and one header credit is equal to the max size header plus optional digest field.

Table 42.  Transmit Flow Control Credit Interface
Signal Name Direction Clock Domain Description
p0_ss_app_st_txcrdt_tvalid Output p0_axi_st_clk tvalid indicates that the credit information on tdata is valid.
p0_ss_app_st_txcrdt_tdata[18:0] Output p0_axi_st_clk

Carries credit limit information and type of credit.

  • Bit [15:0]: Credit Limit Value
  • Bit [18:16]: Credit Type
  • 3'b000: Posted Header Credit
  • 3'b001: Non Posted Header Credit
  • 3'b010: Completion Header Credit
  • 3'b011: Reserved
  • 3'b100: Posted Data Credit
  • 3'b101: Non Posted Data Credit
  • 3'b110: Completion Data Credit
  • 3'b111: Reserved

The following figure shows the credit limit update on the Transmit Flow Control Credit Interface. The credit limit is first initialized to 0 for all the credit types. In the example below, updated credit limit is output from cycle 9 to cycle 14. When the HOST returns the credit after receiving the packet, credit limit is incremented by the number of credits returned. At cycle 16, one posted header credit is returned; at cycle 19, four posted data credit is returned.

Figure 50. Credit Limit Update on Transmit Flow Control Credit Interface