Visible to Intel only — GUID: arj1710990165312
Ixiasoft
Visible to Intel only — GUID: arj1710990165312
Ixiasoft
5.3.4. PCIe* 0 PCI Express* / PCI Capabilities
Parameter | Value | Default Setting | Description | |
---|---|---|---|---|
PCIe* 0 Device | ||||
Maximum payload size supported |
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512 Bytes | Sets the read-only value of the max payload size of the Device Capabilities register and optimizes for this payload size. |
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Enable multiple physical functions |
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False | Enables multiple physical functions. |
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When you set Enable multiple physical functions to True, the following option is available: Total physical functions (PFs) |
1–4 | 1 | Sets the number of physical functions (PFs). The IP can support 1–4 PFs. |
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Enable SR-IOV support |
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False | Enables the SR-IOV support. |
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When you set Enable SR-IOV support to True, the following option is available: Total virtual functions of physical function 0 (PF0 VFs) |
0–256
Note: 256 is the total virtual functions shared among the physical functions.
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0 | Sets the number of virtual functions (VFs) to be assigned to the physical functions (PFs). Example of maximum VFs of the PFs: If PF0 and PF1 is enabled with PF0 VFs set to 200. Maximum PF1 VFs = 256 - 200 = 56. |
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When you set Enable SR-IOV support to True and provide a Total physical functions (PFs) value greater than 1, the following option is available: Total virtual functions of physical function 1 (PF1 VFs) |
0 | |||
When you set Enable SR-IOV support to True and provide a Total physical functions (PFs) value greater than 2, the following option is available: Total virtual functions of physical function 2 (PF2 VFs) |
0 | |||
When you set Enable SR-IOV support to True and provide a Total physical functions (PFs) value greater than 3, the following option is available: Total virtual functions of physical function 3 (PF3 VFs) |
0 | |||
PCIe* 0 Legacy Interrupt Pin Register | ||||
Set Interrupt Pin for PF<n> (where n = 1, 2, 3, etc.) |
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NO INT | Sets Interrupt Pin for PF0.
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PCIe* 0 PTM | ||||
Enable PTM |
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False | When selected, Precision Time Measurement (PTM) Capability is available for PCIe* 0. |
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When you set Enable PTM to True, the following option is available: Period between each automatic update of PTM context (in ms) |
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Disable | Determines the PTM context auto-update interval. Selecting Disable prevents PTM context auto-update. |
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PCIe* 0 MSI | ||||
PF0 Enable MSI |
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False | Enables MSI functionality for PF0. If you turn on this parameter, the PF0 Number of MSI messages requested parameter appears, which allows you to set the number of MSI messages. | |
If you set PF0 Enable MSI to True, the following options are available: | PF0 MSI Extended Data Capable |
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False | Enables or disables the MSI extended data capability for PF0. |
PF0 MSI 64-bit addressing |
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False | Enables or disables the MSI 64-bit addressing for PF0. | |
PF0 Number of MSI messages requested |
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1 | Sets the number of messages that the application can request in the multiple message capable field of the Message Control register. | |
PCIe* 0 MSI-X | ||||
PCIe* 0 PF MSI-X | ||||
Enable MSI-X |
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False | Enables or disables the MSI-X functionality. | |
Table size | 0x0–0x7FF (only values of powers of two minus 1 are valid) |
0 | Sets the number of entries in the MSI-X table. The system software reads this field to determine the MSI-X table size <n>, which is encoded as <n-1>. For example, a returned value of 2047 indicates a table size of 2048. This field is read-only. Address offset: 0x068[26:16]. |
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Table offset | 0x0–0x1FFFFFFF | 0x00000000 | Points to the base of the MSI-X table. The lower 3 bits of the table BAR indicator (BIR) are set to zero by software to form a 64-bit qword-aligned offset This field is read-only after being programmed. |
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Table BAR indicator | 0x0–0x7 | 0 | Specifies which one of a function's BARs, located beginning at 0x10 in the Configuration Space, is used to map the MSI-X table into memory space. This field is read-only after being programmed. |
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PBA BAR indicator | 0x0–0x7 | 0 | Specifies the function's Base Address register, located beginning at 0x10 in the Configuration Space, that maps the MSI-X PBA into memory space. This field is read-only after being programmed. |
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Pending bit array (PBA) offset | 0x0–0x1FFFFFFF | 0x00000000 | Used as an offset from the address contained in one of the function's Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only after being programmed. |
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PCIe* 0 PASID | ||||
PCIe* 0 PF0 enable PASID |
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False | Enables the PASID (Process Address Space ID) Optional feature, which allows a single endpoint to be shared by multiple processes by provided each a virtual 64-bit address space PCIe* 0 PF0. | |
When you set PCIe* 0 PF0 enable PASID to True, the following options are available: | PCIe* 0 PF0 Enable Execute Permission Support |
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False | Enables or disables the PASID Execute Permission Support for PCIe* 0 PF0. |
PCIe* 0 PF0 max PASID width | 0–20 | 0 | Sets the maximum PASID width for PCIe* 0 PF0. | |
PCIe* 0 PF0 enable Privileged Mode Support |
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False | Enables or disables the PASID Privileged Mode Support for PCIe* 0 PF0. | |
PCIe* 0 DEV SER | ||||
Enable Device Serial Number Capability |
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False | Enables Device Serial Number Capability (DEVSER) optional extended capability is 64-bit that is unique for any given PCIe* device. | |
Device Serial Number (DW1) | 32 bits value | 0x0000_0000_0000_0000 | Sets the lower 32 bits of IEEE 64 bit Device Serial Number (DW1). | |
Device Serial Number (DW2) | 32 bits value | 0x0000_0000_0000_0000 | Sets the upper 32 bits of IEEE 64 bit Device Serial Number (DW2). |