GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

2.1. Supported Features

The GTS AXI Streaming IP supports the following features:

PCI Express* Features

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as Hard IP.
  • Supported configurations are listed in the table below:
    Table 1.  Configurations Supported by the GTS AXI Streaming IP
    Port Mode PCIe* 3.0/ PCIe* 4.0 x8 PCIe* 3.0/ PCIe* 4.0 x4 PCIe* 3.0/ PCIe* 4.0 x2 PCIe* 3.0/ PCIe* 4.0 x1
    Endpoint (EP) Yes Yes Yes Yes
    Root Port (RP)
    Transaction Layer Packet (TLP) Bypass Mode
    Note: PCIe* 1.0/ PCIe* 2.0 speeds are supported through link down-training.
  • Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS)
    • Separate Reference Clock with No Spread Spectrum Clocking (SRNS)
    • Common reference clock architecture
  • Single Virtual Channel (VC)
  • Capability Registers:
    • Message Signaled Interrupt (MSI)
    • Message Signal Interrupt Extended (MSI-X)
    • Advanced Error Reporting (AER) (PF only)
    • Power Management (ASPM, D0 and D3 PCIe* power states) (PF only)
    • Alternative Routing ID (ARI)
    • Address Translation Services (ATS)
    • Page Request Service (PRS)
    • Transaction Processing Hints (TPH)
    • Access Control Services (ACS)
    • Latency Tolerance Reporting (LTR)
    • Process Address Space ID (PASID)
    • Vendor Specific Capability
  • Supports up to 512-byte maximum payload size (MPS)
  • Supports up to 4096-byte (4 KB) maximum read request size (MRRS)
  • 32/64-bit BAR support (Prefetchable/Non-Prefetchable)
  • Expansion ROM BAR support
  • 10 bit Tag Support as requester (x8 controller only)
  • Number of tags
    • x4 controller: 32, 64, 128, 256
    • x8 controller: 32, 64, 128, 256, 512
  • Main data path parity protection
  • ECRC generation and checking
  • MSI-X Table in the GTS AXI Streaming IP (up to 2048 vectors per function)
  • Supports device serial number capability
  • Atomic operations (Fetch/Add/Swap/CAS)
  • Supports relaxed ordering on receive side
  • Support TLP Bypass mode
    • Supports upstream port and downstream port
    • Supports autonomous hip mode
    • No Configuration-via-Protocol (CvP) init/update support
  • Precision Time Measurement (PTM)
  • Support for scaled flow control credits
  • PCIe* 4.0 retimer aware PCIe* controller
  • Support link equalization for PCIe* 3.0 and above speed
  • FPGA core configuration through PCIe* link (CvP init)
  • FPGA core configuration update through PCIe* link (CvP update)
  • Supports autonomous Hard IP mode—This mode allows the PCIe* Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
    Note: Unless Readiness Notifications mechanisms are used, the Root Complex or system software must allow at least 1.0 second after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • Provided to extend the configuration capabilities beyond the PCI* / PCIe* capabilities and implement Customer Specific Capabilities.
  • Supports Application Error Reporting: The GTS AXI Streaming IP implements Application Error Reporting registers. These registers allow you to indicate various errors. The GTS AXI Streaming IP logic then forwards this error information to Hard IP block (UR/CA/Completion Timeout/Poison).
  • Transaction ordering, deadlock avoidance.
    Note: You must implement transaction ordering in user application logic.
  • Debug Toolkit for register accesses and debug (optional).
  • The Quartus® Prime generated design examples.

Multi-function and Virtualization Features (Optional)

  • Single Root I/O Virtualization (SR-IOV) support (maximum 4 PFs, 256 VFs)
  • Supports single TLP prefix per TLP
  • Supports VirtIO PCI* Configuration Registers
  • Scalable IOV
  • Function level reset (FLR)

User Interface Features

  • AXI4-Stream Transmit (TX) interface
    • The AXI4-Stream TX interface comprises the primary signals, and provides the start of the transaction
    • Single Stream interface
  • AXI4-Stream Receive (RX) interface
    • The AXI4-Stream RX interface comprises the secondary signals, and provides the response to the transaction from the TX
    • Support for basic bare metal mode (for example, single physical function, AER, and others) and virtualization mode (for example, multiple physical functions, function level reset, and others)
  • AXI4-Stream Bandwidth
    • Scalable frequency.
    • The operating frequency selection options of 200, 250, 300, or 350 MHz.
  • Control and Status Responder Interface
    • This is the AXI4-Lite Control and Status Interface to access registers implemented in the GTS AXI Streaming IP modules, including PCI* / PCIe* Configuration Registers of all Functions.
    • 32-bit data width at 100–250 MHz.
  • Configuration Intercept interface
    • The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior.
  • Supports Link Partner Credits is exposed through the Transmit Flow Control Credit interface. The credits are advertised as limit value specified in the PCIe* specification. You must check the availability of credits for transmitting the TLP. The Receive side operates on the AXI-Stream ready-valid handshake.
  • Control Shadow Interface provided to shadow the control information from the control/command registers (Optional).
  • Completion timeout interface (Optional)—The GTS AXI Streaming IP can optionally track outgoing non-posted packets to report the completion timeout information to the application.