GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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7.6.5.1. TPH Requester Enhanced Capability Header

Address: Offset 0x0

This register contains the PCI Express* Extended Capability ID for TPH Requester Capability, the capability version, and the pointer to the next capability structure.

Table 120.  Transaction Processing Hints (TPH) Requester Enhanced Capability Header Description
Bit Location Description Attributes Default
15:0 PCI Express* Extended Capability ID. RO Same as parent PF
19:16 Capability Version. RO Same as parent PF
31:20

Next Capability Pointer.

Points to ATS Capability when preset, NULL otherwise.

RO Programmable