GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

7.6. Virtual Function (VF) PCI Express* Configuration Space

Table 104.  VF Configuration Register Address Map
Offset Registers
0x0 – 0x34 VF PCI-Compatible Configuration Space Header Type0
0x70 – 0xA0 VF PCI Express* Capability Structure
0xB0 – 0xB8 VF Message Signal Interrupt Extended (MSI-X) Capability Structure
0x100 – 0x104 VF Alternative Routing ID (ARI) Capability Structure
0x110 – 0x108 VF Transaction Layer Packet (TLP) Processing Hints Capability Structure
0x19C – 0x1A0 VF Address Translation Services (ATS) Capability Structure
0x200 – 0x208 VF Access Control Services (ACS) Capability Structure