GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

7.6.1.2. Command Registers

Address: Offset 0x4

This address contains the PCI Command Register.

Table 105.  Command Register Description
Bit Location Description Attributes Default
0 Reserved RO 0
1 Reserved RO 0
2

Bus Master enable.

Enables the VF to generate transactions as a bus master.

You must obtain this information from configuration intercept interface.

RW 0
5:3 Reserved RO 0
6 Parity Error Enable RsvdZ 0
7 Reserved RO 0
8 System Error Enable RsvdZ 0
15:9 Reserved RO 0