GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 5/15/2024
Public

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Document Table of Contents

1.1. About PCI Express*

PCI Express* is a point-to-point, serial interconnect bus with protocol stack that includes Transaction, Data Link and Physical Layer. The protocol is scalable – from 1 lane to 32 lanes per link, with data on the link serialized and sent from one device to another. It uses differential signaling with complementary pair of signals for transmit and receive sides and uses packet-based transactions.

You can use the Intel FPGA IPs for PCI Express* available in the Quartus® Prime Pro Edition catalog to implement PCI Express* in your designs.

Figure 1.  PCI Express* Topology