GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

4.17.6. ECRC

In the TLP Bypass mode, the ECRC is not generated or stripped by the Agilex™ 5 PCIe* Hard IP by default, that is, you must insert and check ECRC if it is required, by appending.