Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents

3.9. Example Designs

Table 24.  Example Designs

Parameter

Value

Description

Available Example Designs

DMA

PIO

When you select the DMA option, the generated example design includes a direct memory access application. This application includes upstream and downstream transactions.

When you select the PIO option, the generated design includes a target application including only downstream transactions.

Simulation On/Off When On, the generated output includes a simulation model.
Synthesis On/Off When On, the generated output includes a synthesis model.
Generated HDL format

Verilog/VHDL

Verilog HDL and VHDL are supported

Select Board

Intel® Arria® 10 FPGA GX Development Kit

Intel® Arria® 10 FPGA GX Development Kit ES2

None

Specifies the Intel® Arria® 10 development kit.

Select None to download to a custom board.

Note: Currently, you cannot target an Intel® Cyclone® 10 GX Development Kit when generating an example design.