External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021

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3.1.7. PHY Clock Tree

Dedicated high-speed clock networks drive I/Os in Intel® Cyclone® 10 external memory interfaces. Each PHY clock network spans only one bank.

The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

All Intel® Cyclone® 10 external memory interfaces use the PHY clock trees.