External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.21. cal_debug_out_clk for DDR3

User calibration debug clock interface

Table 29.  Interface: cal_debug_out_clkInterface type: Clock Output
Port Name Direction Description
cal_debug_out_clk Output User clock domain