External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
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4.1.1.22. clks_sharing_master_out for DDR3

Core clocks sharing master interface

Table 30.  Interface: clks_sharing_master_outInterface type: Conduit
Port Name Direction Description
clks_sharing_master_out Output This port should fanout to all the core clocks sharing slaves.