External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Document Table of Contents Communication

Communication between the EMIF Toolkit and external memory interface connections is achieved using a JTAG Avalon® -MM master attached to the sequencer bus.

The following figure shows the structure of EMIF IP with JTAG Avalon® -MM master attached to sequencer bus masters.

Figure 91. EMIF IP with JTAG Avalon-MM Master

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