2. External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP Introduction
You can easily implement the EMIF IP core functions through the Intel® Quartus® Prime software. The Intel® Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA.
The External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP (referred to hereafter as the Intel® Cyclone® 10 EMIF IP) provides the following components:
- A physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
- A memory controller which implements all the memory commands and protocol-level requirements.
For information on the maximum speeds supported by the external memory interface IP, refer to the External Memory Interface Spec Estimator.
Intel® Cyclone® 10 GX Protocol Support
The Intel® Cyclone® 10 GX External Memory Interfaces IP provides DDR3 and LPDDR3 external memory protocol support for Intel® Cyclone® 10 GX GX devices.
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