External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public
Document Table of Contents
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4.1.2.1. pll_ref_clk for LPDDR3

PLL reference clock input

Table 42.  Interface: pll_ref_clkInterface type: Clock Input
Port Name Direction Description
pll_ref_clk Input PLL reference clock input