External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2.14. emif_usr_reset_n for LPDDR3

User clock domain reset interface

Table 55.  Interface: emif_usr_reset_nInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion