External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public

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10.7.2.2. Access Protocol

The On-Chip Debug Port provides access to calibration data through an Avalon® -MM slave interface. To send a command to the sequencer, user logic sends a command code to the command space in sequencer memory. The sequencer polls the command space for new commands after each group completes calibration, and continuously after overall calibration has completed.

The communication protocol to send commands from user logic to the sequencer uses a multistep handshake with a data structure as shown below, and an algorithm as shown in the figure which follows.

typedef struct_debug_data_struct {
...
// Command interaction
alt_u32 requested_command;
alt_u32 command_status;
alt_u32 command_parameters[COMMAND_PARAM_WORDS];...
}

To send a command to the sequencer, user logic must first poll the command_status word for a value of TCLDBG_TX_STATUS_CMD_READY, which indicates that the sequencer is ready to accept commands. When the sequencer is ready to accept commands, user logic must write the command parameters into command_parameters, and then write the command code into requested_command.

The sequencer detects the command code and replaces command_status with TCLDBG_TX_STATUS_CMD_EXE, to indicate that it is processing the command. When the sequencer has finished running the command, it sets command_status to TCLDBG_TX_STATUS_RESPONSE_READY to indicate that the result of the command is available to be read. (If the sequencer rejects the requested command as illegal, it sets command_status to TCLDBG_TX_STATUS_ILLEGAL_CMD.)

User logic acknowledges completion of the command by writing TCLDBG_CMD_RESPONSE_ACK to requested_command. The sequencer responds by setting command_status back to STATUS_CMD_READY. (If an illegal command is received, it must be cleared using CMD_RESPONSE_ACK.)

Figure 103. Debugging Algorithm Flowchart