External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021

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3.1.8. PLL Reference Clock Networks

Each I/O bank includes a PLL that can drive the PHY clock trees of that bank, through dedicated connections. In addition to supporting EMIF-specific functions, such PLLs can also serve as general-purpose PLLs for user logic.

External memory interfaces that span multiple banks use the PLL in each bank. The Intel® Cyclone® 10 architecture allows for relatively short PHY clock networks, reducing jitter and duty-cycle distortion.

In a multi-bank interface, the clock outputs of individual PLLs must remain in phase; this is achieved by the following mechanisms:

  • A single PLL reference clock source feeds all PLLs. The reference clock signal reaches the PLLs by a balanced PLL reference clock tree. The Intel® Quartus® Prime software automatically configures the PLL reference clock tree so that it spans the correct number of banks.
  • The IP sets the PLL M and N values appropriately to maintain synchronization among the clock dividers across the PLLs. This requirement restricts the legal PLL reference clock frequencies for a given memory interface frequency and clock rate. The parameter editor automatically calculates and displays the set of legal PLL reference clock frequencies. If you plan to use an on-board oscillator, you must ensure that its frequency matches the PLL reference clock frequency that you select from the displayed list. The correct M and N values of the PLLs are set automatically based on the PLL reference clock frequency that you select.
Note: The PLL reference clock pin may be placed in the address and command I/O bank or in a data I/O bank, there is no implication on timing.
Figure 10. PLL Balanced Reference Clock Tree