External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Document Table of Contents DQ/DQS/DM Deskew

To get the package delay information, follow these steps:
  1. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox on the Board Settings tab of the parameter editor.
  2. Generate your IP.
  3. Instantiate your IP in the project.
  4. Compile your design.
  5. Refer to the All Package Pins compilation report, or find the pin delays displayed in the <core_name>.pin file.

Did you find the information on this page useful?

Characters remaining:

Feedback Message