External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.5. caltiming0

address=31(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_act_to_rdwr 5 0 Activate to Read/Write command timing. Read
cfg_t_param_act_to_pch 11 6 Active to precharge. Read
cfg_t_param_act_to_act 17 12 Active to activate timing on same bank. Read