4.3.2. AFI Write Sequence Timing Diagrams
Write sequences with wlat=0
For half rate and quarter rate, when the write command is sent on the first memory clock in a PHY clock (for example, afi_cs_n = 0), that access is called aligned access; otherwise it is called unaligned access. You may use either aligned or unaligned access, or you may use both, but you must ensure that the distance between the write command and the corresponding write data are constant on the AFI interface. For example, if a command is sent on the second memory clock in a PHY clock, the write data must also start at the second memory clock in a PHY clock.
The following diagrams illustrate both aligned and unaligned access. The first three write commands are aligned accesses where they were issued on LSB of afi_command. The fourth write command is unaligned access where it was issued on a different command slot. AFI signals must be shifted accordingly, based on the command slot.
Write sequences with wlat=non-zero
The afi_wlat is a signal from the PHY. The controller must delay afi_dqs_burst, afi_wdata_valid, afi_wdata and afi_dm signals by a number of PHY clock cycles equal to afi_wlat, which is a static value determined by calibration before the PHY asserts cal_success to the controller. The following figures illustrate the cases when wlat=1. Note that wlat is in the number of PHY clocks and therefore wlat=1 equals 1, 2, and 4 memory clocks delay, respectively, on full, half and quarter rate.
The afi_dqs_burst signal must be asserted one or two complete memory clock cycles earlier to generate DQS preamble. DQS preamble is equal to one-half and one-quarter AFI clock cycles in half and quarter rate, respectively.
The following diagrams illustrate how afi_dqs_burst must be asserted in full, half, and quarter-rate configurations.
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