External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Document Table of Contents

3.1.9. Clock Phase Alignment

A global clock network clocks registers inside the FPGA core, and the PHY clock network clocks registers inside the FPGA periphery. Clock phase alignment circuitry employs negative feedback to dynamically adjust the phase of the core clock signal to match the phase of the PHY clock signal.

The clock phase alignment feature effectively eliminates the clock skew effect in all transfers between the core and the periphery, facilitating timing closure. All external memory interfaces employ clock phase alignment circuitry.

Figure 11. Clock Phase Alignment Illustration

Figure 12. Effect of Clock Phase Alignment

Clock Phase Alignment Timing Diagrams

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