External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public
Document Table of Contents

4.1.1.19. cal_debug_clk for DDR3

User calibration debug clock interface

Table 27.  Interface: cal_debug_clkInterface type: Clock Input
Port Name Direction Description
cal_debug_clk Input User clock domain

Did you find the information on this page useful?

Characters remaining:

Feedback Message